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    • 专利摘要:
    Process for producing a transistor in which: a) at least one semiconductor structure formed of a stack comprising an alternation of layer (s) (12, 12 ', 12' ') based on a substrate is produced at least one first semiconductor material and layer (s) (16, 16 ') based on at least one second semiconductor material different from the first semiconductor material, b) amorphous implantation aid, zone of the structure, the amorphous zone comprising one or more portions (161, 16'1) of one or more layers based on the second semiconductor material, c) the portions (161, 16'1,) by selective etching of the second semiconductor material rendered amorphous with respect to the first semiconductor material
    公开号:FR3033934A1
    申请号:FR1552111
    申请日:2015-03-16
    公开日:2016-09-23
    发明作者:Sylvain Barraud；Shay Reboh；Maud Vinet
    申请人:Commissariat a lEnergie Atomique CEA；Commissariat a lEnergie Atomique et aux Energies Alternatives CEA；
    IPC主号:
    专利说明:

    [0001] TECHNICAL FIELD The present invention relates to the field of microelectronics and more particularly to that of transistors, and relates to the production of a transistor formed by the invention. BACKGROUND OF THE INVENTION in a stack of superimposed semiconductor layers. It applies to the realization of a transistor having a semiconductor channel region having a plurality of semiconductor elements distributed over several levels, these semiconductor elements can be in the form of nano-son, or bars, or membranes. It more particularly allows an improved implementation of a transistor having such a channel region and a coating gate disposed around the semiconductor elements. PRIOR ART The realization of a transistor whose channel structure is formed of a plurality of nano-wires distributed over several levels is known. A method of manufacturing such a transistor may include forming a stack of semiconductor layers comprising alternating Si-based layers and SiGe-based layers.
    [0002] Then, in particular, selectively removing the SiGe with respect to the Si, so as to release the nano-Si son before depositing the gate of the transistor. With such a method, to allow free nano son of Si while ensuring a maintenance of the structure, binding design rules must generally be applied.
    [0003] Because of these design rules, the bulk of source and drain blocks is important and does not allow the implementation of a large density of 3033934 2 nano-son. Moreover, a good positioning and a good definition of the grid pattern is difficult to obtain. Another method of producing a nano-son transistor is to form the gate by a damascene method. In such a process, a cavity 2 of gate material is filled after having carried out a nano-son release step, for example by selectively etching nano-wires of SiGe with respect to nano-wires 4 of Si A disadvantage of such an approach is that it is difficult to avoid over-etching SiGe which may tend to reach regions in which the source and drain of the transistor are provided. Such an example of over-etching is illustrated in FIG. 1. This over-etching can result in an imprecise and non-uniform arrangement of the grid which is then produced in the cavity 2. This can cause, in particular, an increase parasitic capacitances. More generally, there is the problem of finding a new method for producing a transistor formed in a stack of superimposed semiconductor layers. SUMMARY OF THE INVENTION According to one aspect, the invention provides a method of making a transistor formed in a stack of superimposed semiconductor layers, the method comprising the steps of: a) providing on a substrate, at least a semiconductor structure formed of a stack comprising an alternation of layer (s) based on at least one first semiconductor material and layer (s) based on at least one second different semiconductor material of the first semiconductor material, b) amorphous by means of one or more implantations of ions, at least one zone of the structure, the amorphous zone comprising one or more portions of one or more layers based on of the second semiconductor material, 3033934 3 c) removing the portions based on the second amorphous semi-conductor material by selective etching of the second semiconductor material in amorphous form with respect to the first semi-conductive material ucteur. A first embodiment provides that the area rendered amorphous in step b) is located in a central region of the structure in which a channel region of the transistor is apt to be formed. In this case, the method may furthermore comprise, after step a) and prior to step b), the formation of masking on the stack, the masking comprising an opening revealing a central region of the structure, the amorphization implant (s) being then made through the opening of the masking, so that the amorphous zone is located in the opening while the crystalline structure of parts of the layer (s) based on of the second semiconductor material which are protected by masking and are located outside the aperture. The withdrawal of the portions may then be carried out in step c) by selectively etching the second semiconductor material in amorphous form with respect to the layers based on the first semiconductor material and parts of the layers based on the second semiconductor material whose crystal structure has been preserved in step b). Such selective etching may make it possible to avoid inadvertent over-etching of the structure. Then, we can form a grid in the opening in which we made the amorphization. Advantageously, this opening may be an opening of a masking made before step b) by: - forming a sacrificial gate arranged on the central region, then - forming a masking layer against the sacrificial gate of to form the masking, - formation of the opening in the masking by removal of the sacrificial gate.
    [0004] A precise alignment of the grid can thus be obtained.
    [0005] According to a first possible embodiment, the amorphization in step b) may be a selective amorphization of the portions based on the second semiconductor material vis-à-vis the layers based on the first semiconductor material, and in particular, portions of the layers based on the first semi-conductive material which are located in the opening. To enable such selective amorphization, the implantation parameters are adapted and the first semiconductor material and the second semiconductor material are suitably selected. The first semiconductor material may be in particular Si-based or Si-x-Gex (with x> 0), while the second semiconductor material is Si-SiGey-based with x <y. The amorphization selectivity can be adapted by modulating the difference in Germanium concentration between the first semiconductor material and the second semiconductor material. Selective amorphization can be achieved through several implantations at different depths of the structure. According to a second possibility of implementation, the amorphization in step b) may be a partial amorphization of the central region of the structure so as to render amorphous one or more portions of one or more layers based on the second material semiconductor and one or more portions of given layers 20 based on the first semiconductor material which are in the opening while retaining the crystal structure of at least one layer based on the first semiconductor material unveiled also by opening. After removal of the portions of the second semiconductor material rendered amorphous in step c), at least one recrystallization thermal annealing step may be carried out. The portions of the given layers based on the first semiconductor material can thus be recrystallized. A second embodiment provides that the region rendered amorphous in step b) is located in regions of the structure in which source and drain regions of the transistor are able to be formed, the implantation or implantations being carried out. in step b) so as to maintain the crystalline structure of a central region of the structure in which a channel region of the transistor is adapted to be realized. In this case, a withdrawal of the portions based on the second semiconductor material in amorphous form is then carried out by selective etching of the second semiconductor material in amorphous form with respect to the layers based on the first semiconductor material and portions of the second semiconductor material-based layer or layers located in the central region and whose crystalline structure has been preserved. The removal of the portions based on the second semiconductor material 10 in amorphous form can lead to the formation of empty spaces. The method may then further comprise steps of: depositing a given material in the empty spaces, the given material being a material chosen so that the second semiconductor material in amorphous form is capable of being selectively etched vis-à-vis the given material. Forming a mask with an opening revealing the central region of the structure; removing portions based on the second semiconductor material in the aperture by selective etching of the second semiconductor material with respect to of the first semiconductor material and the given material.
    [0006] The given material may advantageously be an insulating material. Such selective etching may make it possible to avoid inadvertent over-etching of the structure. In step b), a sacrificial gate may be provided on the central region of the structure. In this case, the method may further comprise forming a masking layer against the sacrificial gate so as to form a masking, and then withdrawing the sacrificial gate to form an opening in the masking. It is then through this opening that we can perform the step c) of removing the parts based on the second semiconductor material. A grid may then be deposited in the opening after step c).
    [0007] The method may further comprise after step c) at least one thermal annealing step so as to re-crystallize the layers based on the first semiconductor material. In either embodiment, the stack made may comprise an alternation of Sii, Gex-based layer (s), and Si x Ge y-based layers with 0 x <y. This stack may advantageously be formed on a SOI or SiGe01 type substrate. According to another aspect, the invention provides a method for producing a transistor formed in a stack of superimposed semiconductor layers, the method comprising the steps of: providing on a substrate at least one semiconductor structure formed of a stack comprising an alternation of layer (s) based on at least one first semiconductor material and layer (s) based on at least one second semiconductor material different from the first semiconductor material. conductor, - removing in a central region of the structure disclosed by an opening of a masking portions based on the second semiconductor material, the removal being carried out: - by selective etching of the second semi-conductor material made amorphous in the l opening with respect to the first semiconductor material, or else - by selective etching of the second semiconductor material vis-à-vis the first semiconductor material and a donating material born surrounding the second material out of the opening and previously formed. This given material may be formed by amorphization using one or more implantations of zones of the structure disposed on either side of the central region, then etching in these zones of the second semiconductor material in amorphous form. and replacing the second semiconductor material in amorphous form with a given material. This given material is chosen so as to resist selective etching of the second semiconductor material.
    [0008] The material given is advantageously an insulating material. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be better understood on reading the description of exemplary embodiments given, purely by way of indication and in no way limiting, with reference to the appended drawings, in which: FIG. 1 illustrates a problem of overgraving susceptible to appear during a process for producing a nano-son channel structure implemented according to the prior art; Figs. 2A-20 illustrate a first exemplary method of making a transistor according to an embodiment of the present invention; FIGS. 3A-3C illustrate a second example of a method for producing a transistor according to an embodiment of the present invention; Figs. 4A-4H illustrate a third exemplary method of making a transistor according to an embodiment of the present invention; Identical, similar or equivalent parts of the different figures bear the same numerical references so as to facilitate the passage from one figure to another. The different parts shown in the figures are not necessarily in a uniform scale to make the figures more readable.
    [0009] In addition, in the following description, terms which depend on the orientation, such as "on", "above", "upper", "lateral" etc. of a structure apply considering that the structure is oriented in the manner illustrated in the figures. DETAILED DESCRIPTION OF PARTICULAR EMBODIMENTS An exemplary method of making a transistor formed in a stack of superimposed semiconductor layers will now be described in conjunction with FIGS. 2A-20.
    [0010] FIG. 2A illustrates a possible starting material for this exemplary method in the form of a semiconductor-on-insulator type substrate, for example of the SOI type, which comprises a semiconducting support layer, an insulating layer, which may be based on silicon oxide and is disposed on and in contact with the support layer 10. The insulating layer 11 of the substrate may in particular be a BOX-type layer (BOX for "Burried Oxide") based on an insulator such as SiO2. A thick BOX layer for example of the order of 145 nm may be provided. The substrate also comprises a semiconductive layer 12 located on and in contact with the insulating layer 11 of the substrate. The superficial semiconductor layer 12 is based on a first crystalline semiconductor material 13. The first semiconductor material 13 may be Sii_xGex with x 0. In this embodiment, the first semiconductor material 13 may be silicon (x = 0). Several other semiconductor layers are formed on the superficial semiconductor layer 12, for example by several successive epitaxies, and form with it a semiconductor stack. The semiconductor stack may be formed of an alternation of one or more layers 12, 12 ', 12 "based on the first semiconductor material 13 and one or more layers 16, 16', based on a second semiconductor material 17 different from said first semiconductor material The second semiconductor material 17 may be based on Sii_yGey 20 with a concentration y in Germanium different from that of the first crystalline semiconductor material 13 and y which For example, a stack of at least two semiconductor layers can be provided, eg a stack with a number of semiconductor layers 12, 16, 12 ', 16', 12 ". non-limiting example in Figure 2C.
    [0011] The layers 12, 12 ', 12 "based on the first semiconductor material 13 may have a thickness e1 of, for example, between 5 and 25 nanometers, for example of the order of 12 nm. based on the second semiconductor material 17 may have a thickness e2 for example between 5 and 25 nanometers, for example of the order of 12 nm.
    [0012] Once the stack has been made, the layers 12, 12 ', 12 ", 16, 16' of the latter are etched so as to produce at least one structure 18 formed of superimposed semiconductor elements based on the first semilimic material. 13 and the second semiconductor material 17. The semiconductor elements may be, according to their width W, for example in the form of nano-wires, or bars, or membranes, the width W of the semiconductor elements may be For example, in the example of FIG. 2C, W is measured in a direction parallel to the main plane of the substrate, the main plane of the substrate being between several nanometers and several tens of nm, for example of the order of 10 nm. , being a plane passing through the substrate and parallel to the plane [0; x; y] of an orthogonal reference [0; x; y; z]. The semiconductor elements of this structure 18 can be provided to connect a first block and a second block intended to form respectively a source region and a drain region of the transistor. The source and drain regions are in this embodiment of the etched blocks of the structure 18 made at the same time as the semiconductor elements. In the example of Figure 2C, several juxtaposed structures 18 each formed of a stack of nano-son, or bars, or membranes are made. The distance D between two juxtaposed structures 18 may be for example between 20 and 50 nanometers, for example of the order of 30 nm. To make or structures 18, photolithography and etching techniques can be employed. Then, on a central region of the nano-son structures 18, a sacrificial gate 20 is formed. This sacrificial gate 20 covers an upper face 18a, otherwise known as the top of the structures 18, as well as the lateral flanks 18b, 18c of the central region of the structures 18 (FIG. 2D). To form this gate 20 can be deposited at least one gate dielectric 21, for example based on 5i02 that is covered with at least one layer of gate material 22 for example such as polysilicum. The gate dielectric 21 may have a thickness of several nanometers, for example between 2 and 6 nm. The gate material 22 can have a thickness of several tens of nanometers, for example between 50 and 200 nm. The dielectric 21 and the gate material 22 are then etched through masking, which may be in the form of a hard mask.
    [0013] The hard mask may for example be based on silicon nitride and may have a thickness between several nm and one or more tens of nm, for example of the order of 40 nm. In FIG. 2E, the sacrificial gate 20 covering a central region of the structures 18 is represented in a view from above, without the hard mask.
    [0014] Insulating spacers 27 may then be formed against the sacrificial gate 20 and the hard mask 25. The insulating spacers 27 may be made by depositing an insulating layer, for example based on silicon nitride (SiN, SiBCN, for example , or 5i02) to the level of the hard mask 25 and then by etching of this insulating layer.
    [0015] Then, particularly by epitaxial growth, a semiconductor material 30 can be formed on the source and drain blocks (FIG. 2F). The semiconductor material 30 formed may be, for example, silicon-carbon SiC: P or silicon Si: P, in particular for implementing an NMOS transistor. Doping of the semiconductor material 30, for example with phosphorus (P), can also be carried out. This doping can be performed in situ during epitaxy. The semiconductor material 30 covers an upper face of the source and drain regions and may also cover side faces (not shown in the cross-sectional view of Fig. 2F) of the source and drain regions. To implement a PMOS transistor, silicon germanium doped with boron could be used Sii_xGex: B (with for example 25 x> 0.2). Doping can then also be performed in situ during epitaxy. Then, a masking layer 40 is formed so as to cover the structures 18 and the hard mask 25. The masking layer 40 may be chosen based on a material that can be etched selectively with respect to that of the hard mask 25. This masking layer 40 may for example be based on silicon oxide.
    [0016] A step of removal, for example by planarization or CMP polishing (CMP for "Chemical Mechanical Planarization"), of this masking layer 40 is then performed with a stop at the top or the upper face 25a of the hard mask 25. The upper face 25a of the hard mask 25 is thus unveiled (e) at the end of this withdrawal step (Figure 2G). Then, it is made in the masking layer 40 by making an opening 45 by removal of the hard mask 25 and the sacrificial gate 20. The opening 45 can extend to the insulating layer 11 of the substrate and reveal the side faces 18b, 18c structures 18 at their central region. The opening 45 may have a constant section and retain the exact imprint of the sacrificial gate 20. The removal of the material 22 from the sacrificial gate 20 can be achieved for example by wet etching with a solution of TMAH (Tetramethylammonium hydroxide), when the material 22 is polySi. The dielectric 21 is then removed. Thus, in the opening 45, a central region of the structures 18 is not covered by another material (FIG. 21 in which the device is shown in a view from above). At least one region of the central region of the structures 18 is then amorphized using one or more ion implantations (FIG. 2J and 2K). In this example, a selective amorphization of portions 161, 161 'of the layers 16, 16' based on the second semiconductor material 17 which are revealed by the opening 45 with respect to portions 121, 121 ', 121 is carried out. "layers 12, 12 ', 12" based on the second semiconductor material 17 which are unveiled by the opening 45. The parts 121, 121', 121 "are thus not rendered amorphous and retain their crystalline structure (FIG. 2L).
    [0017] The amorphization selectivity may be due to the choice of the semiconductor materials 13 and 17 as well as that of one or more of the implantation parameters (s) which are the dose, the energy and the implantation temperature. . The pair of semiconductor materials 13 and 17 is preferably selected so that the implantation dose required to amorphize the second semiconductor material 17 is lower than the dose required to amorphize the first semiconductor material. In this example, an amorphization selectivity can be obtained in particular by virtue of a difference in Ge concentration between the first semiconductor material 13 and the second semiconductor material 17. Thus, for the same given dose of implantation and the same given temperature, only the layer 16 based on the second semiconductor material 17 rich in Ge is amorphized. This selectivity in the amorphization is for example described in the document: "Amorphization threshold in Si implied strained SiGe alloy rents", of T.W. Simpson et al., EMRS 94, Boston. In order to obtain a good amorphization selectivity, the difference in concentration y-x between the first crystalline semiconductor material 13 and the second semiconductor material 17 is preferably greater than or equal to 15%.
    [0018] Those skilled in the art will be able to obtain experimental curves with a difference in concentration of Ge given, the dose, the energy and the implantation temperature to obtain a selective amorphization. In fixed dose and energy, the temperature at which the substrate is placed can in particular be adapted to modify the amorphization selectivity.
    [0019] The Simpson document referred to above gives, for example, windows of temperature and dose to allow, for a given energy, to selectively amorphize Sii_yGey with y = 0.15 with respect to Si or to allow, for a given energy to selectively amorphize Sii_yGey with y = 0.29 with respect to Si.
    [0020] FIG. 6 of this document shows that placing itself above a first implantation limit temperature given by the abscissa of the "Si" curve and below a second implantation limit temperature given by the abscissa of the "15% Ge" curve, the Sii_yGey can be amorphized with y = 0.15 without amorphizing Si. The species used to amorphize the second crystalline semi-conductive material 17 may be, for example, Si.
    [0021] The implantation energy and the dose depend on the depth at which the portions 161, 16'1 of the layers 16, 16 'to be amorphous are situated. In order to be able to render amorphous layers 16, 16 'located at different heights of the structure 18, an implantation or several implantations 5 carried out according to different energies and respective implantation doses can be performed. In one embodiment, several implantations are performed at different implanting energies, each energy being adapted so as to provide a maximum concentration of defects at the portions 161, 16'1 of the layers 16, 16 '. of the second semiconductor material 17. The amorphization of the different portions 161, 16'1 of layers based on the second semiconductor material 17 can be performed in a sequence of implantations made from the highest to the lowest energy. The corresponding doses may be adapted for the different implantations, given the different implantation depths, and may take into account the dose accumulation provided by the sequential implantation. For example, to render a SixGel layer amorphous, with x = 0.6, with a thickness of the order of 8 nm situated at a depth of about 30 nm of a semiconductor stack without amorphous layers of If located respectively under and in contact, and on and in contact with the SixGel_x layer, an implantation of Si at an energy of 25 keV and a dose of 1.5 x 10 14 cm -2 can be used. According to one variant, by adapting the dose-implantation energy pair, the amorphization can be carried out in a single ion implantation. For example, the document "Se amophization of ion-bombarded SiGe strained-layer superlattices", de Vos et al., Applied Physics Letter 58 (9), 1991, shows that SixGe1-x layers can be selectively implanted into a stack of Si layers and SixGel-x layers. In this example, maintaining the crystalline structure of the portions 121, 121 ', 121 "based on the first semiconductor material may in particular prevent further recrystallization of these portions 121, 121', 121". . This subsequent recrystallization is likely to generate defects in the semiconductor material. After the selective amorphization, the portions 161, 16'1 of the layers 16, 16 'based on the second semiconductor material 17 located inside the opening 45 are removed (FIG. 2M). This shrinkage can be achieved by selective etching of the portions 161, 16'1 based on the second semiconductor material 17 in amorphous form vis-à-vis the rest of the layers 16, 16 'based on the second semiconductor material 17 under crystalline form and the first semiconductor material 13 (FIG. 2L). Nano-wires or bars or suspended membranes based on the first semiconductor material are thus released. Such selective etching may be carried out for example by means of dry etching, for example using HCl, or HBr / He / O2 or HBr / Cl2 or CF4 / HBr / C12) or wet. for example using HF / H202 acetic chemistry, or SC1 (SC1 for "Standard Clean 1") SC1, diluted, SC1 being a mixture of water / hydrogen peroxide (H 2 O 2) / ammonia (NH 4 OH ). when the second material 17 is based on silicon germanium and when the first semiconductor material 13 is Si. Thus, in the opening 45, semiconductor portions 121, 121 ', 121 "suspended on the basis of first void material 47 are thus formed around these portions, in particular at the locations where the portions 161, 16'1 have been removed Due to the etching selectivity between the amorphous portions 161, 16'1 layers 16, 16 'and portions of these layers outside the aperture and whose crystalline form has been preserved, void spaces 47 are accurately defined and over-relief as illustrated in FIG. 1 is avoided Next, a gate is formed in the opening 45 (FIGS. 2N and 20) The formation of this gate 50 may comprise the deposition of a gate dielectric 51 such as, for example, HfO 2, then at least one material 52 of grid that can be metallic, pa TiN-based example or formed of a stack of metal material 30 and semiconductor material such as polysilicon. Thus, the opening 45 is filled and a coating grid 50 is formed filling the empty spaces around the semiconductor portions 121, 121 ', 121 ". The gate 50 produced may be of GAA type (acronym for" Gate All Around "). A step of removing the gate material protruding above the aperture 45 can then be performed.After this step, a self-aligned grid whose dimensions are defined by those of the opening 45 The transistor that is realized in this example is thus provided with a channel semiconductor structure formed of a plurality of semiconductor elements, such as nano-wires or bars or diaphragms. , placed one above the other and thus distributed over several levels, a coating grid being provided around these elements According to another exemplary embodiment, a method as described above can be implemented from a stack form alternating a first Si-xGex-based semiconductor material 13 with x for example such that 0 x <0.1 and a second semiconductor material 17 based on Sii_yGey with y> x and y greater than 0.3, preferably such that yx> 0.15 advantageously such that yx> 0.5. Selective amorphization by implantation of a Sii_yGey layer with a concentration Ge of the order of 30% using a dose for example of the order of 2x10 'ions / cm 2 can then be performed. Another exemplary embodiment adapted in particular to implement a PFET type transistor can provide as a starting material a SiGe01-type substrate, in which the superficial semiconductor layer 12 is based on Sii_yGey with y 0 and for example such that y = 0.2.
    [0022] In this case, the semiconductor stack which is then produced may be formed of an alternation of layers 12, 12 ', 12 "based Sii_yGey and layers 16, 16' based on Si or Sii, Gex with x> y (x = 0.5 and y = 0.2, for example) The same steps are then carried out as in the example of the process described above, in particular portions of the layers being amorphized in particular. , 16 ', while maintaining the crystalline structure of the layers 12, 12', 12 ". Then, the amorphized portions of the layers 16, 16 'are selectively etched. Thus nano-wires or bars or suspended membranes based on Sii_yGey are formed. According to a variant of the exemplary method which has just been described with reference to FIGS. 2A-20, instead of the step of selective amorphization of the central region of the structure or structures 18 located in the opening 45 described above in connection with FIGS. 2J-2L, amorphizing the whole of this central region or preferably a zone Z of this central region while maintaining the crystalline structure at least one semiconductor layer 12 based on the first semiconductor material 13.
    [0023] Thus, in the embodiment of FIG. 3A, amorphization of portions 121 ", 121 ', layers 12", 12' based on the first semiconductor material 13 as well as amorphization of portions 161 are carried out. ', 161, layers 16', 16, based on the second semiconductor material 17 which are in the opening 45.
    [0024] This amorphization can be carried out with the aid of an implantation provided in particular by its dose and its energy so as to preserve the crystalline structure of a layer 12 base of the first semiconductor material 13, in this example of the layer the lowest of the semiconductor stack. Selective removal of the second amorphous rendered material (FIG. 3B) (etching HCl, or HBr / He / O2 or HBr / Cl2 or CF4 / HBr / C12 or by HF / H202 acetic acid chemistry, Hot SC1, SC1 diluted) is then carried out. . A recrystallization annealing can then be performed. This annealing can be carried out at a high temperature, for example at a temperature of between 700 ° C. and 1050 ° C. in order to restore a crystalline structure to the portions 121 ", 121 ', layers 12", 12'. This recrystallization can be carried out by a specific annealing step (FIG. 3C) or can be carried out during the formation of the grid 50, and in particular during an annealing intended to stabilize the gate dielectric. Another alternative embodiment of the method will now be described with reference to FIGS. 4A-4D.
    [0025] For this process, after having realized the semiconductor structure 18 in the stack of alternating layers 12, 12 ', 12 "based on the first semiconductor material 13 and layers 16, 16' to Based on the second semiconductor material 17, a sacrificial gate is produced on a central region of the semiconductor structure 18. This sacrificial gate can be made, for example, in a manner similar to the sacrificial gate 20 previously described in FIG. Thus, formation of the sacrificial gate 20 may include etching a gate stack through a hard mask 25.
    [0026] Then, zones Z1, Z2 of the stack disposed on either side of the central region of the structure 18 on which the sacrificial gate 20 rests are amorphous. In this example, the amorphous zones Z1, Z2 can contain regions of the stack in which the source and drain regions of the transistor are provided. Thus, portions 162, 163, 16'2, 16'3 are amorphized based on the second semiconductor material 17 as well as portions 122, 123, 12'2, 12'3, 12 "2, 12" 3 to base of the first semiconductor material. An alternative is to amorphize only the portions 162, 163, 16'2, 16'3 based on the second semiconductor material 17 leaving the portions 122, 123, 12'2, 12'3, 12 "2, 12" 3 crystalline based on the first semiconductor material.
    [0027] This amorphization can be carried out using at least one (or more) ion implantation (FIG. 4B). During implantation, the hard mask 25 disposed on the grid may serve as an implantation mask so as to protect the central region of the structure 18. This preserves the crystal structure of this central region.
    [0028] Then, the portions 162, 163, 16'2, 16'3 are removed from the zones Z1, Z2 based on the second semiconductor material made amorphous selectively with respect to the portions 122, 123, 12'2, 12'3, 12 "2, 12" 3 based on the first semiconductor material. This removal can be achieved for example by etching the second semiconductor material 17 in amorphous form. This etching is selective towards the second semiconductor material 17 in its crystalline form and vis-à-vis the first semiconductor material 13 in its crystalline form and in its amorphous form. Thus empty spaces 147 are defined between the layers 12, 12 ', 12 "based on the first semiconductor material 13. Because of the etching selectivity, these empty spaces 147 extend precisely to the central region of the structure 18 which comprises portions of the layers 12, 12 ', 12 ", 16, 16' whose crystal structure has been preserved (FIG. 4C). The empty spaces 147 are then filled by a given material 157, which may be for example a dielectric material (FIG. 4D). The material given is a material chosen so that the second semiconductor material 17 can be etched with respect to this given material 157. The given material 157 may be for example based on silicon nitride (SiaNb) or oxide (SiO2) when the second semiconductor material is Sii_yGey. The insulating spacers 27 can then be formed against the sacrificial gate 20 and the hard mask 25. Then, the semiconductor material 30 is formed by epitaxial growth on the source and drain blocks. The masking layer 40 is then made (FIG. 4E). The opening 45 is then formed by removing the hard mask 25 and the sacrificial gate 20 (FIG. 4F).
    [0029] Portions 161, 16'1 are removed from the layers 16, 16 'based on the second semiconductor material 17 located inside the opening 45 (FIG. 4G). This shrinkage can be achieved this time by selective etching of the portions 161, 16'1 based on the second semiconductor material 17 in crystalline form vis-à-vis the given material 157 in contact with these portions 161, 16'1 and of the first semiconductor material 13. Nano-wires or bars or suspended membranes based on the first semiconductor material 13 are thus released. Such selective etching may be carried out for example by means of a dry etching. (HCl, HBr / He / 02 or HBr / C12 or CF4 / HBr / C12 etching) or wet (HF / H202 acetic chemistry, Hot SC1, SC1 diluted) when the second material 17 is removed 3033934 19 opening 45 is based on silicon germanium and when the materials 13 and 157 are respectively Si and silicon nitride (or silicon oxide 5i02). Thus, in the opening 45, semiconductor portions 121, 121 ', 121 "based on the first semiconductor material 13, some 121', 121" are suspended.
    [0030] A recrystallization annealing, making it possible to restore a crystalline structure to the portions 122, 123, 12'2, 12'3, 12 "2, 12" 3 based on the first semiconductor material, can then be carried out before the formation of a crystalline structure. gate 50, or during the realization of this grid 50 encapsulating in the opening 45 and being arranged around the semiconductor portions 121, 121 ', 121 "(Figure 4H).
    [0031] According to one variant of one or the other of the examples of the method which have been described previously in connection with FIGS. 3 and 4, the transistor can be provided in a stack formed of an alternation of semiconductor materials different from those given in the previous examples. A method as described above is particularly applicable to the implementation of channel structure MOSFETs formed of nano-son distributed on several levels and coating gate. This grid can be formed in particular after nano-son release (so-called "gate last" approach). A transistor obtained by means of a method as described above can be included for example in a logic circuit with high performance and low consumption, or for example in memory, in particular a NAND Flash memory, a memory molecular, or for example in a sensor such as a charge detector. 25
    权利要求:
    Claims (13)
    [0001]
    REVENDICATIONS1. A method of making a transistor formed in a stack of superimposed semiconductor layers, the method comprising the steps of: a) providing on a substrate at least one semiconductor structure (18) formed of a stack comprising a alternating layer (s) (12, 12 ', 12 ") based on at least one first semiconductor material (13) and layer (s) (16, 16') based on at least one second semiconductor material (17) different from the first semiconductor material, b) amorphous by means of one or more implantations, at least one zone (Z1, Z2, R, R ') of the structure (18) the amorphous region comprising one or more portions (161, 16'1, 162, 16'2, 163, 16'3) of one or more layers based on the second semiconductor material (17), c) removing the portions (161, 16'1, 162, 16'2, 163, 16'3) by selective etching of the second semiconductor material (17) rendered amorphous with respect to the first semiconductor material (13).
    [0002]
    The method of claim 1, wherein the amorphous rendered area (R, R ') in step b) is located in a central region of the structure (18) in which a channel region of the transistor is adapted to be formed, the method further comprising, after step a) and prior to step b): - forming a masking on the stack, the masking comprising an opening (45) unveiling a central region of the structure ( 18), the implant (s) in step b) being made through the opening (45) of the masking, so that the rendered area (R, R ') is amorphous located in the opening (45) while the crystalline structure of portions of the layer or layers based on the second semiconductor material located outside the opening (45) is retained, the portion removal being then carried out in step c) by selective etching of the second semiconductor material (17) in amorphous form vis-à-vis the layers based on the prem ier semiconductor material (13) and portions of the one or more layers based on the second semiconductor material (17) whose crystal structure has been preserved in step b), and then after step c), forming a grid (50) in the opening (45).
    [0003]
    3. The method according to claim 2, wherein the amorphization in step b) is a selective amorphization of the portions (161, 16'1) based on the second semiconductor material (17) with respect to layers (12, 12 ', 12 ") based on the first semiconductor material (13).
    [0004]
    4. The method of claim 3, wherein the first semiconductor material (13) is based on Si or Sii, Gex (with x> 0), the second semiconductor material (17) being based on Sii_yGey with 0 x <y.
    [0005]
    5. The method of claim 2, wherein the amorphization in step b) is a partial amorphization of the central region of the structure (18) so as to amorphize one or more portions (161, 16'1, 162). , 16'2, 163, 16'3) of one or more layers based on the second semiconductor material (17) and furthermore one or more layers (12 ', 12 ") given based on the first semi material -conductor (13) while maintaining the crystalline structure of at least one layer (12) based on the first semiconductor material (13).
    [0006]
    6. Method according to claim 5, comprising after removal of the portions in step c), at least one thermal annealing step so as to re-crystallize the given layers (12 ', 12 ") based on the first semi-crystalline material. conductor (13) 3033934 22
    [0007]
    7. Method according to one of claims 2 to 6, wherein the masking is performed prior to step b) by forming a sacrificial gate (20) arranged on the central region of the structure, and forming a masking layer against the sacrificial gate so as to form the masking, then forming the opening (45) in the masking by removal of the sacrificial gate.
    [0008]
    The method of claim 1, wherein the amorphous region (Z1, Z2) is located in regions of the structure in which source and drain regions of the transistor are formed, where the implantations are performed in step b) so as to preserve the crystalline structure of a central region (R) of the structure (18) in which a channel region of the transistor is capable of being produced, the withdrawal in step c) portions are then made by selective etching of the second semiconductor material (17) in amorphous form with respect to the layers based on the first semiconductor material (13) and portions of the at least one second semiconductor material (17) located in the central region and whose crystalline structure has been preserved.
    [0009]
    9. The method of claim 8, wherein the shrinkage of the portions results in the formation of voids (147), the method further comprising steps of: depositing a given material (157) in the void spaces (147), - formation of a mask having an opening (45) revealing the central region of the structure, - removing portions (161, 16'1) based on the second semiconductor material in the opening by selectively etching the second semiconductor material vis-à-vis the first semiconductor material and the given material (157). 3033934 23
    [0010]
    The method according to claim 9, wherein in step b), a sacrificial gate (20) is arranged facing the central region, the method further comprising forming a masking layer against the sacrificial gate ( 20) so as to form the masking, the opening (45) being made by removal of the sacrificial grating.
    [0011]
    11. Method according to one of claims 8 to 10, further comprising after step c) at least one thermal annealing step so as to re-crystallize the layers based on the first semiconductor material (13). o
    [0012]
    12. Method according to one of claims 1 to 11, wherein the stack comprising an alternation of layer (s) (12, 12 ', 12 ") based Sii, Gex, and layers Sii_yGey with 0 x <y 15
    [0013]
    13. Method according to one of claims 1 to 12, wherein the stack is formed on a SOI or SiGe01 type substrate.
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    同族专利:
    公开号 | 公开日
    US20160276494A1|2016-09-22|
    EP3070744B1|2017-07-05|
    US9876121B2|2018-01-23|
    FR3033934B1|2017-04-07|
    EP3070744A1|2016-09-21|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1552111A|FR3033934B1|2015-03-16|2015-03-16|IMPROVED METHOD FOR REALIZING A TRANSISTOR IN A STACK OF SUPERIMPOSED SEMICONDUCTOR LAYERS|FR1552111A| FR3033934B1|2015-03-16|2015-03-16|IMPROVED METHOD FOR REALIZING A TRANSISTOR IN A STACK OF SUPERIMPOSED SEMICONDUCTOR LAYERS|
    EP16160138.0A| EP3070744B1|2015-03-16|2016-03-14|Improved method for producing a transistor in a stack of superposed semiconductor layers|
    US15/070,781| US9876121B2|2015-03-16|2016-03-15|Method for making a transistor in a stack of superimposed semiconductor layers|
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